This job ad has been posted over 40 days ago.
2
applicants
JD-12 ASIC Verification Engineer
at www.amarverma.com in Bangalore
Seeking highly motivated, team-oriented individuals interested in verification of complex networking ASIC’s. Individual will be working with an experienced and motivated team to address exciting opportunities.
Responsibilities
- Define test plan and verification methodology.
- Develop full chip and block level test bench in C++/System Verilog environment.
- Technically lead the team for developing test cases, running regressions and monitoring coverages.
Qualifications *Experience in System Verilog or equivalent verification language
- Working knowledge of Network protocols(Ethernet/IP/TCP)
- Experience in ASIC methodologies and tools (synthesis, timing and formal verification)
- Experience in C/C++ and scripting languages like PERL or TCL.
- Experience with verilog RTL coding.
- BSEE/CS with 6+ years of experience
About www.amarverma.com:
www.amarverma.com
Phone: 009027929703
Published at 07-03-2010
Viewed: 229 times
Viewed: 229 times
